Final project of Integrated circuit design (CENG465, undergraduate class), Spring 2025: design, simulate, and verify flip flops at layout level from circuits in IEEE papers

Luke Valerio, B.S. EE Chapman University, 2025; M.S. ECE University of Washington, Seattle

Instructor: Peiyi Zhao, Ph.d, Associate Professor, www1.chapman.edu/~zhao

IC design in this project was performed using the following tools:
Cadence Virtuoso for schematic and layout creation, Synopsys Hspice for simulation, Siemens Calibre for layout verification.

The process involved designing a flip-flop circuit based on an IEEE paper. The design flow included the following:
Schematic capture in Virtuoso, followed by layout creation.
Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification were conducted using Calibre to ensure layout correctness and connectivity matching the schematic.
Parasitic capacitances were extracted using Calibre's parasitic extraction (PEX) feature integrated within Virtuoso.
Post-layout simulations were carried out in Hspice to verify circuit functionality through waveform analysis.
Power consumption was measured at different processing corners, operating at 1 GHz frequency, 1 V supply voltage, and 10% switching activity, targeting a 45 nm technology node.
This project involved considerable debugging.

Acknowledgement: Thanks to Dr. Michael Fahy for his strong support of the above CAD tools!

Paper 1: G. Shin, E. Lee, J. Lee, Y. Lee and Y. Lee, "An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination," in IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3039-3048, Oct. 2021.

Function: Reduces power consumption by reducing clock signals through only updating the clkb signal if there is a change to the input D

Here is the vertical schematic:

Here is the horizontal layout I created:

Here is the layout's waveform:

Paper 2: H. You, J. Yuan, Z. Yu and S. Qiao, "Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 5, pp. 1022-1032, May 2021.

Function: Reduces power consumption by eliminating redundant precharge operations and enabling retentive, true single-phase-clock operation; Only updating the clkb signal if there is a change to the input D.

Here is the vertical schematic:

Here is the horizontal layout I created:

Here is the layout's waveform: